Semiconductor packaging process using through silicon vias

ABSTRACT

A microelectronic unit  400  can include a semiconductor element  401  having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts  403  at the front surface and a rear surface remote from the front surface. The semiconductor element  401  can have through holes  410  extending from the rear surface through the semiconductor element  401  and through the contacts  403 . A dielectric layer  411  can line the through holes  410 . A conductive layer  412  may overlie the dielectric layer  411  within the through holes  410 . The conductive layer  412  can conductively interconnect the contacts  403  with unit contacts.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of the filing date of U.S. Provisional Patent Application No. 60/962,752, filed Jul. 31, 2007, the disclosure of which is hereby incorporated by reference herein.

BACKGROUND OF THE INVENTION

Microelectronic devices generally comprise a thin slab of a semiconductor material, such as silicon or gallium arsenide, commonly called a die or a semiconductor chip. In one face of the die is fabricated the active circuitry. To facilitate electrical connection to the active circuitry, the die is provided with bond pads on the same face. The bond pads are typically placed in a regular array either around the edges of the die or, for many memory devices, in the die center. The bond pads are generally made of a conductive metal, such as gold or aluminium, around 0.5 μm thick. The size of the bond pads will vary with the device type but will typically measure tens to hundreds of microns on a side.

Wire bonding and flip-chip interconnection are two schemes used for making contact to the die bond pads. In wire bonding, the die is attached to a substrate in a face-upwards orientation and fine wire is connected to each bond pad by a solid state joining method such as ultrasonic welding or thermo-compression diffusion bonding. In flip-chip interconnection, lumps of metal are placed on each bond pad. The die is then inverted so the metal lumps provide both the electrical pathway between the bond pads and the substrate as well as the mechanical attachment of the die to the substrate. There are many variations of the flip-chip process, but one common configuration is to use solder for the lumps of metal and fusion of the solder as the method of fastening it to the bond pads and the substrate. When it melts the solder flows to form truncated spheres. Depending on the dimensions of the solder sphere this is referred to as a ball grid array (BGA) interface or a micro ball grid array (μBGA) interface.

Semiconductor devices used as image sensors usually require a face-up orientation such that the scene of interest can be focused (or projected) on the active circuitry. For commercial reasons, it is often desirable that the die are connected to the substrate using a BGA or μBGA interface.

One approach to connect the die bond pads on the front face of the die to a BGA interface on the rear face of the die is to provide wiring traces that extends from the die bond pads over the front face of the die, down the sides of the die and onto the rear face of the die. This type of lead contact is often referred to as a “T-style contact” because the wiring trace on the edge of the die and the wiring trace on the front face of the die appears to form a “T” where they join. FIGS. 2 a and 2 b illustrate an example of a T-style contact.

FIG. 2 a shows a schematic frontal 200 view and FIG. 2 b a cross-sectional view 250 of a single T-style contact of a semiconductor package. The die is drawn upside down so the front face 201/251 is towards the bottom of the page and the rear face 202/252 towards the top of the page. A bond pad 203/253 on the front face connects to the wiring trace 204/254 on the edge of the die. The wiring trace continues to a land 205/255 on the rear face, where it joins to a solder sphere 206/256. The shape of the T-style contact 257 is evident in the cross-sectional view, while the sidewall angle 207 is indicated in the frontal view. The drawing is not to scale.

An alternative approach for an image sensor package is to use through silicon vias (TSV) to connect the bond pads to the BGA interface. FIG. 3 is a cross-section view 300 of a typical TSV. The TSV is a hole (or blind via) extending through the thickness of the semiconductor that terminates on the underside of a bond pad 304. The sides or wall of the through hole are coated with metal to form an electrically conductive pathway between the front and rear surfaces of the die. A deep reactive ion etching process known in the engineering community as the ‘Bosch process’ may be used to form the TSV shown in FIG. 3. The contact to the bond pad 304 shown in FIG. 3 is often described as U-style. To complete the electrical circuit between the underside of the die bond pads and the conductive coating applied to the walls of TSVs requires a solid state bond between the two metals.

FIG. 3 shows the semiconductor die inverted with a front face 301 and a rear face 302. A hole 310 extends through the thickness of the die and the dielectric film 303 underneath the bond pad 304 to terminate on the bond pad 304. A dielectric material 311 and a conductive coating 312 line the walls of the hole. Both the dielectric material lining the through hole 310 and the conductive coating 312 extend on to an area of the rear face 302 of the die. Hole 310 extending through the silicon is parallel-sided and perpendicular to the die faces 301 and 302.

SUMMARY OF THE INVENTION

In an embodiment of the present invention, a microelectronic unit can include a semiconductor element having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts at the front surface and a rear surface remote from the front surface. The semiconductor element can have through holes extending from the rear surface through the semiconductor element and through the contacts. A dielectric layer can line the through holes. A conductive layer may overlie the dielectric layer within the through holes. The conductive layer can conductively interconnect the contacts with unit contacts.

In another embodiment of the invention, a microelectronic unit can include a semiconductor element having a front surface, a plurality of contacts at the front surface and a rear surface remote from the front surface. The rear surface can include at least one recess. A plurality of through holes can extend from the recess through the semiconductor element and through the contacts. Conductive vias within the through holes can interconnect the contacts with conductors within the at least one recess.

In still another embodiment of the present invention, a microelectronic unit can include a plurality of semiconductor elements stacked and joined together. Each semiconductor element can have a front surface defining a horizontal plane, contacts at the front surface and a rear surface remote from the front surface. The semiconductor elements can be stacked in a vertical direction transverse to the horizontal plane. A plurality of through holes can extend through at least one of the stacked semiconductor elements and through contacts of the at least one semiconductor element. The contacts of the plurality of stacked semiconductor elements can be exposed within the through holes. A dielectric layer can line the through holes and a conductive layer can overlie the dielectric layer within the through holes. The conductive layer can be in conductive communication with unit contacts of the microelectronic unit.

In an embodiment of the present invention, a microelectronic unit can include a semiconductor element having a front surface, contacts at the front surface, a rear surface remote from the front surface, and edges extending between the front and rear surface. A dielectric element can extend outwardly from at least one of the edges of the semiconductor element. The dielectric element can have a front surface and a rear surface remote from the front surface and can include a plurality of conductive pads connected to the contacts. The dielectric element can also include a plurality of through holes extending between the front and rear surfaces and through the plurality of conductive pads. A plurality of unit contacts can be exposed at an exterior of the microelectronic unit. Conductive features can extend from the contacts within the through holes and can be in conductive communication with the unit contacts.

In another embodiment of the present invention, a method of forming a unit contact exposed at a rear face of a microelectronic element can include forming a first through hole extending from a rear face of the microelectronic element towards an element contact at a front face of the microelectronic element. An insulative coating can be formed overlying at least a wall of the first hole. A second hole can be formed to extend through the element contact. The unit contact exposed at the rear face can be formed including a conductive material which can overlie the wall of the first hole and can overlie a wall of the second hole and be conductively connected with the element contact.

In still another embodiment of the present invention, a method of forming a unit contact exposed at a rear face of a microelectronic element can include (a) forming a through hole extending from a rear face of the microelectronic element through an element contact at a front face of the microelectronic element. An insulative layer can be exposed at a wall of the hole. Further, the microelectronic element can include forming the unit contact exposed at the rear face, including a conductive layer overlying the insulative layer and conductively connected with the element contact.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of a semiconductor die having die bond pads on its periphery.

FIG. 2 a is a front (elevational) view and FIG. 2 b is a sectional view illustrating a conventional chip-scale semiconductor package having a T-style contact.

FIG. 3 is a sectional view illustrating a semiconductor package having a through silicon via exposing an underside (inner surface) of a bond pad.

FIG. 4 a is a sectional view illustrating a semiconductor package having a through silicon via, according to one embodiment of the invention.

FIG. 4 b is a corresponding plan view further illustrating the semiconductor package shown in FIG. 4 a.

FIG. 4 c is a sectional view illustrating a variation of the semiconductor package of FIG. 4 a.

FIGS. 4 d-4 h are sectional views illustrating stages in a process of forming a conductive via according to one embodiment of the invention.

FIG. 5 a is a sectional view illustrating a microelectronic unit including a plurality of vertically stacked semiconductor elements, according to one embodiment of the invention.

FIG. 5 b is a sectional view illustrating a microelectronic unit according to a variation of the embodiment illustrated in FIG. 5 a.

FIG. 6 a is a partial plan view illustrating a portion of a reconstituted wafer including a semiconductor element and a dielectric element adjacent to an edge of the semiconductor element, according to one embodiment of the invention.

FIG. 6 b is a corresponding sectional view illustrating conductive traces extending between the semiconductor element and the dielectric element of the reconstituted wafer shown in FIG. 6 a, according to one embodiment of the invention.

FIGS. 7 a-7 b are sectional views of the reconstituted wafer shown in FIGS. 6 a-6 b, further illustrating a through via extending through the dielectric element and a contact thereon.

FIGS. 8 a-8 f are sectional views illustrating stages in a process of forming a conductive via according to one embodiment of the invention.

FIG. 9 is a plan view illustrating a microelectronic unit in which conductive interconnects to multiple bond pads extend through a common opening.

FIG. 10 a is a sectional view illustrating a portion of a wafer and openings in and between two adjacent semiconductor elements, e.g., die, according to one embodiment of the invention.

FIG. 10 b is a corresponding plan view illustrating several adjacent die in the portion of the wafer shown in FIG. 10 a, according to one embodiment of the invention.

DETAILED DESCRIPTION

As used in this disclosure, a contact “exposed at” a surface of a dielectric element may be flush with such surface; recessed relative to such surface; or protruding from such surface, so long as the contact is accessible by a theoretical point moving towards the surface in a direction perpendicular to the surface. As described, for example in co-pending, commonly assigned U.S. patent application Ser. No. 10/949,674, the disclosure of which is incorporated by reference herein, the through conductors may include elements such as solid metallic spheres, solder connections or other metallic elements. Also, contacts may be disposed at the same locations as the through conductors, or at different locations.

FIG. 1 is a perspective drawing or isometric drawing, not to scale, of a typical semiconductor die 100. The die 100 includes a the front face 101, die edges 102 and bond pads 103 arrayed adjacent the die periphery. Not directly visible, but present by implication, are the rear face 104 of the die and the active circuitry 105 buried just below the surface of the front face 101.

Described below is a form of T-style contact between a wiring trace on the edge of a die or the sidewall of a TSV and a bond pad on the front face of a die. This contact can be used to complete an electrical pathway between the die bond pad and a BGA interface on the opposing face of the die. As will be discussed, this structure also affords the possibility of other interconnect configurations including TSVs fabricated, i.e., etched, starting from the front face of the die and double-sided contacts. Some benefits of various embodiments of the invention include high interconnection density per unit area, simple fabrication processes and pathways through the die thickness offering low electrical resistance.

FIGS. 4 a and 4 b illustrate an example of a TSV that extends through a microelectronic element 400 e.g. a silicon die. FIG. 4 a is a cross-section view of a through silicon via TSV formed along a through hole 410 that extends completely through the entire thickness of a semiconductor die. This includes a semiconductor material region 401 of the die, the bond pad 403, and the dielectric film 402 underneath the bond pad 403. A dielectric material, such as an insulative coating, 411 lines a wall 420 of a through hole, extending through the semiconductor region 401. The thickness 416 of the semiconductor region of the die can range from a few tens of microns to several hundred microns. Some semiconductor wafers, for example, have a thickness of 800 microns. A typical bond pad width 415 along the surface (front face) of the die is 100 microns, which typically is the same or similar to the length of the bond pad along the front surface. As illustrated in the plan view of FIG. 4 b, the intersection between the bond pad 403 and the hole 410 optionally is contained entirely within the area of the bond pad 403.

A conductor, which may be in the form of a conductive coating 412 as shown in FIG. 4 a, contacts edges of the bond pad 403 within the through hole 410 and extends through the hole 410 to the rear face 404. The conductive coating 412 can contact an edge of the bond pad 403 exposed by the through hole 410 to form a T-style contact 405. Both the dielectric material 411 lining wall 420 of the through hole 410 and the conductive coating 412 or other conductor optionally extends onto an area of the rear face 404 of the die.

TSVs having vertical sidewalls may present difficulties in processing. Such TSVs may have high aspect ratios, where the height of each TSV exceeds the diameter of the TSV, sometimes by a factor of two or more. When diameters are small, high aspect ratio TSVs can make vapor deposition processes and electrodeposition processes (e.g., electrophoretic coating and various electroplating processes) more difficult to control.

As shown in FIG. 4 c, the hole 410 can have a tapered shape such that the size of the hole increases with increasing distance from the front surface. In such case, the diameter of the hole increases with increasing distance from the front face of the die. Such shape provides for a radially symmetric T-style contact. Formation of a hollow hole through the die, that is parallel-sided and perpendicular to the die surfaces is readily accomplished by any machining process that is not material selective. Examples include, mechanical drilling, laser ablation, and certain wet etches and activated plasma chemistries. Of these, laser ablation may be relatively easy to instigate in volume manufacture owing to the combination of the speed of material removal, coupled with the benefits of soft tooling associated with this process.

Because the machining process used to form the hole penetrates the thickness of the bond pad it exposes virgin metal of the bond pad. This means there is no need for scrupulous cleaning post-machining of the hole and prior to application of the conductive coating on a wall of the hole. This simplifies the processing.

Referring to FIG. 4 d, in a particular embodiment, a hole 410 can be etched in a semiconductor region 401 of the microelectronic element to expose a surface of a dielectric layer 402 between the element contact 403 and the semiconductor region. An insulative layer 411, (FIG. 4 e) can then be formed which extends along a wall 420 of the hole. Thereafter, as illustrated in FIG. 4 f, the hole 410 can be extended through the dielectric layer 402 and the element contact 403. If the insulative layer 411 lines a bottom of the hole when formed, (such as depicted in FIG. 4 e) the process of extending the hole may cause the hole to pass through a portion of the insulative layer 411 (FIG. 4 f). After extending the hole through the element contact 403, conductive material 412 can then be deposited in contact with the element contact 403 and the insulative layer 411 of the hole, as illustrated in FIG. 4 a.

In another embodiment of the present invention, a hole 410 may be formed through the semiconductor region 401, dielectric layer 402 and element contact 403 in a single step, as seen in FIG. 4 g. In such instance, the hole may be formed using laser ablation or drilling. Thereafter, an insulative layer 411 may be formed over just the semiconductor region 401, as seen in FIG. 4 h. Such an insulative layer may be formed using electrophoretic deposition. Next, conductive material 412 can then be deposited in contact with the element contact 403 and the insulative layer 411 of the hole, as illustrated in FIG. 4 a. Such a conductive layer may be formed using chemical vapour deposition, sputtering or physical vapour deposition.

In a variation of the embodiment shown in FIGS. 4 a-4 c, the conductor may be in the form of a solid conductor which fills the hole, or may be in the form of a conductive coating but extend along only a portion of the wall. In another variation, if the rear face of the die already includes a dielectric layer, the dielectric layer lining the hole need not extend onto the rear face of the die.

An advantage of TSVs of the type shown in FIGS. 4 a-4 c is that the resulting interconnect technology is compatible with stacks of die where bond pads on each layer of die are aligned when viewed in plan (FIG. 5 a). A TSV technology that is able to traverse multiple layers of die makes it possible to connect all of these bond pads in parallel in a single process step. A resulting microelectronic unit includes vertically aligned die 501 joined together in a stack, each die having T-style contacts conductively interconnecting the bond pads 502 of each die with unit contacts 504, as illustrated in FIG. 5 a.

FIG. 5 a shows the principal features of the structure by way of illustration and is not to scale. FIG. 5 a is a cross-section drawing through a stack of die 500. In each layer the TSV 510 extends completely through the dies 501 and bond pads 502, so each connection to the bond pad is by a frusto-conical T-style contact. Two additional features are included in this figure by way of completeness. These are the encapsulant 503 that surrounds each die and holds the stack together and the BGA interface 504 on top of the die stack.

Although FIG. 5 a illustrates TSVs having vertical and taperless walls, alternative embodiments may not be exactly vertical and taperless, regardless of whether they pass through a single die or stack of die. The TSVs may be both tapered and deviate from the vertical. The only restriction is that the TSV must be smaller in diameter than the bond pads through which it passes, as illustrated in FIG. 4 b. This maximizes the length of the T-style contact. Also, a TSV formed partially outside of a bond pad risks damaging circuitry on the die. In accordance with the known art the TSVs may, or may not, be filled with dielectric or conductive material, depending on the electrical characteristics desired of the pathway and which will differ for high power and high frequency applications.

Because the TSV traverses the thickness of the silicon and the bond pad, it will be apparent that the structure can be fabricated by machining from either the front or the rear face of the die. Indeed, should other considerations dictate, it is also possible to machine the TSV from both sides with aligned TSVs meeting within the depth of the die. Following completion of the TSV, it is apparent that the die now has bond pads on the front face coupled to lands in an identical location on the rear face. From the point of view of making electrical connection to the die, it is now effectively a double-sided component so it can be mounted in either the face up or face down orientation. Also, if other electrical or electronic parts are attached to one face of the die, this new form of TSV can be used to convey electrical signals from one side of the die to the other, without interacting with the circuitry on the die, provided the bond pad is a dummy feature with no connection to the die circuitry.

As indicated above, the conductive element of the TSV has to be electrically isolated from the semiconductor through which it passes, otherwise the electrical pathways would all be shorted to each other. This is dielectric layer 411 as shown in FIG. 4. This dielectric layer has to be applied after the machining of the hole, but its application must not extend to the exposed metal of the bond pad that will be used to make the T-style contact. There are a number of processes for forming dielectric films that are compatible with this requirement. One is to create a dielectric layer by oxidation of the exposed semiconductor. This works if the semiconductor is silicon, since silica (silicon oxide) is an insulator. Chemistries exist that will oxidize silicon but leave the metal of the bond pad in a metallic state.

In a variation of the above embodiment, FIG. 5 b shows a stacked microelectronic unit in which TSVs 520 extend through a first semiconductor die 511 and bond pads 522 of the first die, the TSVs exposing bond pads 524 at a front face of a second die 512. A dielectric material 516 can be exposed between opposing faces of the two die. A conductive layer 528 conductively interconnects bond pads 522 of the first die, pads 524 of the second die 512 and unit contacts 544 of the unit. In a variation of the embodiment shown in FIG. 5 b, instead of a single first die 511, a plurality of first die can be stacked and interconnected with the second die 512 by conductive layers within TSVs.

FIG. 6 a illustrates a die built in a reconstituted wafer according to one embodiment of the invention. The silicon die 601 is surrounded on at least four faces (five if the underside of the die is covered) by a dielectric material 602. The bond pads 603 on the die 601 are connected by a wiring trace 604 to new bond pads 605 on the dielectric material 602. A partial sectional view along one wiring trace is given in FIG. 6 b 650. In this figure, it can be seen that the wiring trace 654 is isolated from the semiconductor by a dielectric film 652 that is applied to the die as part of its manufacturing process. The dielectric film 652 does not extend beyond the die periphery because the material used to construct the reconstituted wafer and which surrounds the die, is also dielectric in nature.

In a reconstituted wafer the edges of each die usually are surrounded by dielectric material, such as a solidified liquid polymer, for example, a dielectric overmold composition, as shown in FIG. 6 a. The dielectric material may also cover the rear face of each die. The dielectric material 602 does not usually cover the front face of the die 601 but is flush with it. Part of the process of manufacturing the reconstituted wafers is to apply a patterned metal coating to the front face. The function of this wiring trace is to connect the die bond pads to similar pads outside of the die area. These new bond pads are formed of a conductive materials such as metal overlying the dielectric material. For the embodiment shown in FIGS. 6 a and 6 b, the through vias will be formed which extend through the dielectric material 602 surrounding the die. Consequently, the through vias will not require an additional dielectric film to isolate the conductive coating on the via from the dielectric material through which it passes. A simpler, economical process is achieved particularly when through vias are formed en masse with respect to one or more reconstituted wafers or stack of reconstituted wafers. Reconstituted wafers can be used for both single die applications as well as die stacks.

FIGS. 7 a and 7 b illustrate cross-sectional views through a die formed on a reconstituted wafer 700 according to one embodiment of the invention. Reconstituted wafers are discussed in greater detail in PCT App. US08/09207, filed Jul. 25, 2008, entitled, “RECONSTITUTED WAFER STACK PACKAGING WITH AFTER-APPLIED PAD EXTENSIONS,” which claims the benefit of U.S. Provisional App. No. 60/962,200, filed Jul. 27, 2007, entitled, “RECONSTITUTED WAFER STACK PACKAGING WITH AFTER-APPLIED PAD EXTENSIONS,” the disclosures of which are both incorporated by reference herein. Further, additional detail is provided in U.S. patent application Ser. No. 12/143,743, filed Jun. 20, 2008, entitled, “RECONSTITUTED WAFER LEVEL STACKING,”claiming the benefit of U.S. Provisional App. No. 60/936,617, filed Jun. 20, 2007, entitled, “RECONSTITUTED WAFER LEVEL STACKING,” which is also incorporated by reference herein.

Overlying the die face 701 is the die bond pad 702 and its associated dielectric coating 703 on the die. The die is surrounded on its sides and rear face 704 by a dielectric fill 705 of the reconstituted wafer. The through via 710 (FIG. 7 b) is stepped, and has a first through hole 711 and a second through hole 713. The first through hole 711 has a tapered profile to aid deposition of the conductive coating 712 on a wall of the first through hole 711. A second bond pad 714 is formed on a lower surface 715 of the dielectric fill layer 705, the second bond pad 714 being conductively connected to the die bond pad 702. The conductive coating 712 extends along walls of the second through hole 713 in the second bond pad 714. In this way, a via extension in the second through hole 713 makes conductive contact with the second bond pad 714. After application of the conductive coating to this region, the result is a frusto-conical T-style contact between the second bond pad 714 and the via extension 713.

Machining of TSVs through semiconductor die and machining of through vias penetrating dielectric layers may be accomplished by a variety of processes. In some instances a combination of processes may offer manufacturing advantages so that, for example, plasma etching is used to machine through the thickness of the silicon to produce a tapered via and the hole is extended through the bond pad by laser ablation. The resulting structure has the benefit that the taper angle through the silicon aids application of coatings to the wall of the TSV, while the laser ablation can be used to create a small diameter hole through the bond pad. The interconnect can thus have a stepped diameter structure, as illustrated for a die built from a reconstituted wafer in FIG. 7. This increases the alignment tolerances and also permits contact to a bond pad that is smaller in area than the base of the main hole. An additional benefit is that a TSV having a taper angle can generally be produced with a lower ohmic resistance than a purely vertical via, owing to the combination of a larger surface area and increased thickness of metal applied for a given deposition time compared with a parallel-sided via.

Using such a two-step process (FIG. 7) to form the TSV has benefits for certain embodiments of the structure. As referred to above, when the TSV extends through a semiconductor die, it is usually a requirement that the metal on the wall of the TSV is electrically isolated from the semiconductor substrate and any other conductive structures through which it passes, excepting, of course, the bond pad to which connection is sought. An effective and reliable means of applying a continuous and uniform thickness dielectric film to all surfaces of a part, irrespective of whether they are exposed surfaces or obscured by a high aspect ratio via is to electrocoat the dielectric film, e.g., by electrophoretic deposition. Commonly owned U.S. application Ser. Nos. 11/590,616 filed Oct. 31, 2006 and 11/789,694 filed Apr. 25, 2007 describe methods of electrophoretically depositing dielectric layers, over which conductive layers, e.g., traces or other conductive interconnects are then formed. These applications are hereby incorporated by reference herein.

FIGS. 8 a thru 8 f illustrate a process for forming a TSV according to one embodiment of the invention. FIG. 8 f illustrates a cross-sectional view of a TSV extending through semiconductor die according to one embodiment of the invention.

FIG. 8 a illustrates a partial cross-section through a semiconductor die 801. The front face 802 of the die is opposite, i.e., remote from its rear face 803 and includes a bond pad 804 that is isolated from the semiconductor die 801 by a dielectric film 805. The die is shown with protective dielectric film 806 covering all of its features. This film 806 is representative of structures which can be present in certain types of die packages such as, any variety of compliant layers, die attach films, die stacking adhesives, or combination thereof.

FIG. 8 b illustrates forming a first hole extending from the rear surface 802 of the die 801 to the active surface of the die. For one embodiment, the first hole 807 has a bottom surface positioned above the dielectric film 805. A plasma etch process may be used to form a first hole 807 through the thickness of the silicon in accordance with one embodiment. Because the plasma process is material selective, the first hole 807 stops at the dielectric film 805 on which the bond pad 804 sits. The first hole 807 can have a tapered profile, having the largest area at the rear face 803 of the die. Such a tapered profile may aid subsequent coating of its surfaces. For alternative embodiments, first hole 807 may be formed by wet etching or mechanical milling.

FIG. 8 c illustrates forming an insulative coating 808 over the rear surface 803 of the die according to one embodiment. The insulative coating 808 forms an insulative layer within the first hole 807. In one embodiment, a dielectric film, e.g., an electrocoat material, may be applied to the rear face of the die, such as by electrophoretic deposition. By the nature of the electrocoat material this will be conformal and therefore coat the walls of the first hole 807 as well as the dielectric film 805 underneath the bond pad 804. For alternative embodiments, other dielectric films such as solder mask or photo-resist may be used.

FIG. 8 d illustrates forming a second hole 809 extending through the insulative layer 808, dielectric film 805 and bond pad 804 according to one embodiment. As seen in FIG. 8 d, the diameter of the second hole 809 is contained within the bond pad 804.

For one embodiment, laser ablation may be used to form the second hole 809 through the thickness of insulative material 808, the dielectric film 805 and the bond pad 804. If there is nothing over the bond pad, then the result is a through hole. However, in this instance, the front face of the die is covered by a dielectric material 816. In that case, it is possible for the laser ablated second hole to pass through the dielectric film and the bond pad and terminate in the die covering 816, effectively forming a closed hole or a blind hole. For one embodiment, the die covering 816 may be formed of solder mask. Furthermore, the die covering 816 may be used to form the side walls of a cavity between the die and a glass layer (not shown). A stepped through hole 815, through die 801 and bond pad 804, is formed by the first hole 807 and the second hole 809 and extends from the rear surface 803 of the die thru the bond pad 804.

FIG. 8 e illustrates forming a conductive layer 810 that can include metal, according to one embodiment. The conductive layer 810 is then applied to the inside surfaces of the through hole 815 created by the first and second holes. Because the stepped through hole 815 passes through the bond pad 804, it will form a radially symmetric T-style contact 811. The TSV can be formed by coating the holes with metal or by filling the holes with metal.

One process that can be used for applying a metal coating is a vapor phase deposition, examples of which include evaporation and sputtering. These processes will also deposit metal on the rear face of the die. By patterning this film it is possible to create a BGA interface 812 where each site for a solder ball is connected to a via and the die bond pad as seen in FIG. 8 f. The thickness of the applied metal may be substantially increased by about an order of magnitude by additional processing such as electroplating. In another embodiment, the via can be filled completely with an electrically conductive material.

Thereafter, a layer 813 of dielectric material can be deposited overlying the conductive layer 810 in the holes as shown in FIG. 8 f. Exposed metal of the wiring traces can be covered by an organic protective dielectric coating. A common material is solder mask. The completed structure can then appear as shown in FIG. 8 f.

FIGS. 8 a thru 8 f illustrate the formation of vias to provide electrical contact between a bond pad formed on a die and a BGA interface according to an embodiment of the present invention. The holes extend from the rear surface of the diethrough the bond pad. Furthermore, the diameter of the second hole does not extend beyond the perimeter of the bond pads. For alternative embodiments, the first and second holes need not be circular. The first hole can be greatly elongated to form a notch or trench that spans several bond pads. Second holes then pass through bond pads at the base of the notch or trench on a singular basis. This embodiment requires the metal coating on the sidewall of the notch or trench to be patterned unless it is desired that a row of bond pads are connected in parallel. This is sometimes the case for bond pads that supply electrical power to a semiconductor.

Typical dimensions for both die bond pads or bond pads on dielectric regions of reconstituted wafers are in the region of 100 μm on a side. A typical TSV will have a diameter of about 50 μm if parallel-sided, and about 50 μm at the base and about 80 μm at the opening if tapered. The extension of the TSV through the bond pad will be slightly smaller at around 20 μm diameter.

All of the preceding examples refer to the case where one TSV intersects a single bond pad or a stack of bond pads. One reason for this is that the conductive coating on the via is a single sheet of metal and therefore presents one electrical pathway. The technology exists to pattern metal on the interior of vias. Therefore, a single via could be used to intersect and connect to multiple bond pads. In this instance each T-style contact would not be a complete circle or oval, but an arc. This embodiment is illustrated in FIG. 9.

FIG. 9 provides a plan view of a TSV located over four bond pads according to one embodiment of the invention. The TSV has patterned metal on the side walls, permitting a separate pathway to be made to each bond pad. Four bond pads 901, 902, 903 and 904 are exposed at the front face of the die. A tapered via 905 passes through a portion of all four bond pads. The metal on the TSV is patterned 906, 907, 908 and 909 to provide individual arcs of T-style contacts to the bond pads.

Formation of the TSVs is preferably done at the wafer level since it allows all of the structures to be fabricated in parallel, so the process costs are shared among all of the yielding parts. Following completion of such processing, the wafer must be singulated to free individual die. This may be accomplished by mechanical sawing. Alternatively, it can be organised so that when the semiconductor is being machined to form the hole of the TSV, material is also removed from the dicing street, as shown in FIG. 10 a. Singulation then involves removing or cutting through any material present in the dicing street on the front of the wafer, or simply cleaving it. All of these processes are quicker to perform than dicing through the full thickness of the semiconductor plus those layers. Although the TSVs used for electrical connection are preferably circular, it will be apparent that to separate the die on the wafer, the TSVs fabricated in the streets can be in the form of a slot in the street (dicing lane) between each die, as illustrated in FIG. 10 b. The die can remain connected by small ligaments of semiconducting material at each corner as this retains electrical continuity over the entire rear surface of the wafer from a single point of electrical contact. This attribute can be helpful for the next process step which is the application of the electrocoat dielectric film.

FIGS. 10 a and 10 b indicate how a process used to form a TSV can be used to simultaneously remove the semiconductor material from the dicing street (dicing lane), aiding subsequent singulation of die from a wafer according to one embodiment of the invention. Shown in FIG. 10 a is a dicing street 1001 between two adjacent die 1010 and 1020 on a wafer. Each die has a TSV 1011/1021 hole formed through the silicon to the dielectric film 1012/1022 underneath the bond pad 1013/1023. By the same machining process used to form the TSVs that will be used for electrical connections, another TSV 1002 has been fabricated in the dicing street. By removing this portion of the wafer material the die are effectively singulated with out need for a subsequent dicing process. FIG. 10 b is a plan view 1050 of the rear face of several adjacent die on a wafer. Circular TSVs 1051 have been formed to contact each bond pad, while slot-shaped TSVs 1052 have been machined in the dicing streets at the same time as part of the singulation process. Ligaments of semiconductor 1054 remain at each intersection of four die corners to provide the electrical continuity of the wafer face for the subsequent electrocoat process.

Features of the various embodiments described herein can be combined to form microelectronic units having some or all of the features of one described embodiment and one or more features of another described embodiment. Applicants intend by this disclosure to permit all such combination of features, even though such combinations may not be expressly described. 

1. A microelectronic unit, comprising: a semiconductor element having a front surface and a rear surface opposite the front surface, a microelectronic semiconductor device adjacent to the front surface, and contacts at the front surface, the semiconductor element having through holes extending from the rear surface through the semiconductor element and through the contacts, the contacts having outer surfaces facing away from the semiconductor element, and inner surfaces opposite from the outer surfaces, the through holes defining wall surfaces extending within the contacts from the inner surfaces towards the outer surfaces; a monolithic dielectric layer lining portions of the through holes and overlying at least portions of the inner surfaces; and a conductive element overlying the dielectric layer within the through holes, the conductive element contacting at least the wall surfaces within the contacts so as to conductively interconnect the contacts with unit contacts.
 2. The microelectronic unit of claim 1, wherein the semiconductor element further comprises contacts overlying the rear surface.
 3. The microelectronic unit of claim 2, wherein the holes are tapered, the holes becoming smaller with increasing distance from the rear surface.
 4. The microelectronic unit of claim 3, wherein walls of the holes are oriented at an angle of about 5 degrees or greater with respect to a normal to the rear surface.
 5. The microelectronic unit of claim 4, wherein the walls are oriented at an angle of less than or equal to about 40 degrees with respect to a normal to the rear surface.
 6. The microelectronic unit of claim 1, wherein an entire area of each hole is enclosed within an area of one of the contacts.
 7. The microelectronic unit of claim 1, further comprising a dielectric film overlying the inner surfaces of the contacts, wherein the monolithic dielectric layer overlies portions of the dielectric film.
 8. A microelectronic unit, comprising: a microelectronic element having a front surface and a rear surface opposite the front surface, and a plurality of contacts at the front surface; the rear surface including at least one recess; a plurality of through holes extending from the recess through the microelectronic element and through the contacts, the contacts having outer surfaces facing away from the semiconductor element and inner surfaces opposite from the outer surfaces, a dielectric layer lining at least portions of the through holes, the through holes defining wall surfaces extending within the contacts from the inner surfaces towards the outer surfaces; and conductive vias within the through holes, the conductive vias contacting at least the wall surfaces within the contacts so as to interconnect the contacts with conductors within the at least one recess.
 9. The microelectronic unit of claim 8, wherein the conductors are interconnected with unit contacts exposed at locations of the rear surface beyond the at least one recess.
 10. The microelectronic unit of claim 8, wherein the conductive vias are separated from walls of the through holes by the dielectric layer.
 11. The microelectronic unit of claim 8, further comprising a microelectronic device adjacent to the front surface, the contacts being connected to the microelectronic device.
 12. The microelectronic unit of claim 8, wherein the at least one recess includes a plurality of blind holes, each blind hole being registered with at least one of the through holes.
 13. The microelectronic unit of claim 12, wherein the at least one recess includes a plurality of blind holes, each blind hole being registered with a single through hole.
 14. The microelectronic unit of claim 12, wherein each blind hole has a wall oriented at an angle of 5 degrees or greater with respect to a normal to the rear surface.
 15. The microelectronic unit of claim 8, wherein the at least one recess includes an elongated trench, the trench being registered with a plurality of the through holes.
 16. The microelectronic unit of claim 15, wherein each elongated trench has a wall oriented at an angle of 5 degrees or greater with respect to a normal to the rear surface.
 17. The microelectronic unit of claim 8, further comprising a dielectric layer lining a wall of the recess, the conductors being separated from the wall by the dielectric layer.
 18. The microelectronic unit of claim 8, further comprising a dielectric layer separating the contacts from the front surface of the semiconductor element, wherein the through holes extend through the dielectric layer and the conductive vias directly contact walls of the dielectric layer within the through holes.
 19. The microelectronic unit of claim 8, wherein the dielectric layer overlies at least portions of the inner surfaces of the contacts.
 20. The microelectronic unit of claim 19, further comprising a dielectric film overlying the inner surfaces of the contacts, wherein the dielectric layer overlies portions of the dielectric film.
 21. A microelectronic unit, comprising: a plurality of semiconductor elements stacked and joined together, each semiconductor element having a front surface defining a horizontal plane and a rear surface opposite the front surface, and having contacts at the front surface, the semiconductor elements being stacked in a vertical direction transverse to the horizontal plane; a plurality of through holes extending through at least one of the stacked semiconductor elements and through contacts of the at least one semiconductor element, the contacts having outer surfaces facing away from the semiconductor element, and inner surfaces opposite from the outer surfaces, the through holes defining wall surfaces extending within the contacts from the inner surfaces towards the outer surfaces, the contacts of the plurality of stacked semiconductor elements being exposed within the through holes; a monolithic dielectric layer lining portions of the through holes and overlying at least portions of the inner surfaces; and a conductive layer overlying the dielectric layer within the through holes, the conductive layer contacting at least the wall surfaces within the contacts so as to in conductive communication with unit contacts of the microelectronic unit.
 22. The microelectronic unit of claim 21, wherein the unit contacts are exposed at an exterior of the microelectronic unit.
 23. The microelectronic unit of claim 21, wherein the through holes extend through contacts of a plurality of the stacked semiconductor elements.
 24. The microelectronic unit of claim 21, wherein the through holes do not extend entirely through all of the stacked semiconductor elements.
 25. The microelectronic unit of claim 21, wherein the front surface of at least one of the stacked semiconductor elements faces down and the unit contacts are exposed at an upwardly facing top face of the unit.
 26. The microelectronic unit of claim 21, wherein the front surface of at least one of the stacked semiconductor elements faces up and the unit contacts are exposed at an upwardly facing top face of the unit.
 27. The microelectronic unit of claim 21, further comprising a dielectric film overlying the inner surfaces of the contacts, wherein the monolithic dielectric layer overlies portions of the dielectric film.
 28. A microelectronic unit, comprising: a semiconductor element having a front surface, contacts at the front surface, a rear surface remote from the front surface, and edges extending between the front and rear surfaces; a dielectric element extending outwardly from at least one of the edges of the semiconductor element, the dielectric element having a front surface and a rear surface remote from the front surface, the dielectric element bearing a plurality of conductive pads connected to the contacts, the dielectric element having a plurality of through holes extending between the front and rear surfaces and through the plurality of conductive pads; a plurality of unit contacts exposed at an exterior of the microelectronic unit; and conductive features extending from the contacts and within the through holes, the conductive features in conductive communication with the unit contacts.
 29. The microelectronic unit of claim 28, wherein the semiconductor element further comprises contacts overlying the rear surface.
 30. The microelectronic unit of claim 29, wherein the holes are tapered, the holes becoming smaller with increasing distance from the rear surface.
 31. The microelectronic unit of claim 30, wherein walls of the holes are oriented at an angle of about 5 degrees or greater with respect to a normal to the rear surface.
 32. The microelectronic unit of claim 31, wherein the walls are oriented at an angle of less than or equal to about 40 degrees with respect to a normal to the rear surface. 